873
SAM4CP [DATASHEET]
43051E–ATPL–08/14
39.4
I/O Lines Description
39.5
Product Dependencies
39.5.1 I/O Lines
The pins used for interfacing the SLCD Controller may be multiplexed with PIO lines. Please refer to product block
diagram.
If I/O lines of the SLCD Controller are not used by the application, they can be used for other purposes by the PIO
Controller.
By default (SLCDC_SMR0/1 registers cleared) the assignment of the segment controls and commons are automatically
done depending on COMSEL and SEGSEL in SLCDC_MR. As example, if 10 segments are programmed in the
SEGSEL field, they are automatically assigned to SEG[9:0] whereas remaining SEG pins are automatically selected to
be driven by the multiplexed digital functions.
Anyway, the user can define a new layout pattern for the segment assignment by programming the SLCDC_SMR0/1
registers in order to optimize the usage of multiplexed digital function. If at least 1 bit is set in SLCDC_SMR0/1 registers,
the corresponding I/O line will be driven by an LCD segment whereas any cleared bit of this register will select the
corresponding multiplexed digital function.
Table 39-2.
I/O Lines Description
Name
Description
Type
SEG [3:47], SEG49
Segments control signals
Output
COM [0:4]
Commons control signals
Output
Table 39-3.
I/O Lines
Instance
Signal
I/O Line
Peripheral
SLCDC
COM0
PA0
X1
SLCDC
COM1
PA1
X1
SLCDC
COM2
PA2
X1
SLCDC
COM3
PA3
X1
SLCDC
COM4/AD1
PA4
X1
SLCDC
SEG3
PA9
X1
SLCDC
SEG4
PA10
X1
SLCDC
SEG5
PA11
X1
SLCDC
SEG6/AD0
PA12
X1
SLCDC
SEG7
PA13
X1
SLCDC
SEG8
PA14
X1
SLCDC
SEG9
PA15
X1
SLCDC
SEG10
PA16
X1
SLCDC
SEG11
PA17
X1
SLCDC
SEG12
PA18
X1
SLCDC
SEG13
PA19
X1
SLCDC
SEG14
PA20
X1
SLCDC
SEG15
PA21
X1