318
SAM4CP [DATASHEET]
43051E–ATPL–08/14
19.
Reinforced Safety Watchdog Timer (RSWDT)
19.1
Description
When two watchdog timers are implemented in a device, the second one, the Reinforced Safety Watchdog Timer
(RSWDT) works in parallel with the Watchdog Timer (WDT) to reinforce safe watchdog operations.
The RSWDT can be used to reinforce the safety level provided by the Watchdog Timer (WDT) in order to prevent system
lock-up if the software becomes trapped in a deadlock. The RSWDT works in a fully operable mode, independent of the
Watchdog Timer. Its clock source is automatically selected from either the slow RC oscillator clock or main RC oscillator
divided clock to get an equivalent slow RC oscillator clock. If the Watchdog Timer clock source (for example the 32 kHz
crystal oscillator) fails, the system lock-up is no longer monitored by the Watchdog Timer as the second watchdog timer,
RSWDT, will perform the monitoring. Thus, there is no lack of safety irrespective of the external operating conditions.
This RSWDT shares the same features as the WDT (i.e. a 12-bit down counter that allows a watchdog period of up to 16
seconds with slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be
stopped while the processor is in debug mode or idle mode.
19.2
Embedded Characteristics
System safety level reinforced by means of an independent second watchdog timer.
Automatically selected reliable independent clock source other than that of first watchdog timer.
Windowed Watchdog.
12-bit key-protected programmable counter.
Provides reset or interrupt signals to the system.
Counter may be stopped while the processor is in debug state or in idle mode.
19.3
Block Diagram
Figure 19-1.
Reinforced Safety Watchdog Timer Block Diagram
= 0
1
0
set
reset
read RSWDT_SR
or
reset
rswdt_fault
(to Reset Controller)
(ORed with wdt_fault)
set
reset
WDFIEN
rswdt_int
(ORed with wdt_int)
RSWDT_MR
slow RC clock
1/128
12-bit Down
Counter
Current
Value
WDD
RSWDT_MR
<= WDD
WDV
WDRSTT
RSWDT_MR
RSWDT_CR
reload
WDUNF
WDERR
reload
write RSWDT_MR
RSWDT_MR
WDRSTEN
main RC clock
divider
main RC frequency
Automatic selection
[CKGR_MOR.MOSCRCEN=0
and
(WDT_MR. WDDIS
or
SUPC_MR.XTALSEL=1)]
1
0