341
SAM4CP [DATASHEET]
43051E–ATPL–08/14
20.6.6 Supply Controller Wake-up Mode Register
Name:
SUPC_WUMR
Address:
0x400E141C
Access:
Read/Write
FWUPEN: Force Wake-up Enable
0 (NOT_ENABLE) = The force wake-up pin has no wake-up effect.
1 (ENABLE) = The force wake-up pin low forces a system wake-up.
SMEN: Supply Monitor Wake-up Enable
0 (NOT_ENABLE) = The supply monitor detection has no wake-up effect.
1 (ENABLE) = The supply monitor detection forces a system wake-up.
RTTEN: Real-time Timer Wake-up Enable
0 (NOT_ENABLE) = The RTT alarm signal has no wake-up effect.
1 (ENABLE) = The RTT alarm signal forces a system wake-up.
RTCEN: Real-time Clock Wake-up Enable
0 (NOT_ENABLE) = The RTC alarm signal has no wake-up effect.
1 (ENABLE) = The RTC alarm signal forces a system wake-up.
LPDBCEN0: Low-Power Debouncer Enable WKUP0/TMP0
0 (NOT_ENABLE) = The WKUP0/TMP0 input pin is not connected to the low-power debouncer.
1 (ENABLE) = The WKUP0/TMP0 input pin is connected to the low-power debouncer and can force a system wake-up.
LPDBCEN1: Low-Power Debouncer Enable WKUP10/TMP1
0 (NOT_ENABLE) = The WKUP10/TMP1 input pin is not connected to the low-power debouncer.
1 (ENABLE) = The WKUP10/TMP1 input pin is connected to the low-power debouncer and can force a system wake-up.
LPDBCCLR: Low-Power Debouncer Clear
0 (NOT_ENABLE) = A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 (ENABLE) = A low-power debounce event on WKUP0/TMP0 or WKUP10/14/15/TMP1/2/3 (if DISTMPCLR1/2/3 is cleared)
generates an immediate clear on the first half of GPBR registers.
31
–
30
29
28
27
–
26
25
24
DISTSTMP3
DISTSTMP2
DISTSTMP1
DISTMPCLR3
DISTMPCLR2
DISTMPCLR1
23
–
22
–
21
20
19
–
18
17
16
LPDBCEN3
LPDBCEN2
LPDBC
15
–
14
13
12
11
–
10
9
8
WKUPDBC
FWUPDBC
7
6
5
4
–
3
2
1
0
LPDBCCLR
LPDBCEN1
LPDBCEN0
RTCEN
RTTEN
SMEN
FWUPEN