330
SAM4CP [DATASHEET]
43051E–ATPL–08/14
20.4.7 Backup Power Supply Reset
20.4.7.1 Raising the Backup Power Supply
As soon as the backup voltage VDDBU_SW rises, the 32 kHz RC oscillator is powered up and the zero-power power-on
reset cell maintains its output low as long as VDDBU_SW has not reached its target voltage. During this time, the Supply
Controller is entirely reset. When the VDDBU_SW voltage becomes valid and zero-power power-on reset signal is
released, a counter is started for five slow clock cycles, which is the time required for the 32 kHz RC oscillator to stabilize.
After this time, the SHDN pin is asserted high and the core voltage regulator is enabled. The core power supply rises and
the brownout detector provides the core regulator status as soon as the core voltage VDDCORE is valid. The system
reset signal is then released to the Reset Controller after the core voltage status has been confirmed as being valid for at
least one slow clock cycle.
Figure 20-3.
Raising the VDDBU_SW Power Supply
20.4.7.2 SHDN Output Pin
The SHDN pin is designed to drive the enable pin of an external voltage regulator. This pin is controlled by the VROFF bit
in SUPC_CR. When the device goes into backup mode (VROFF written to 1), the SHDN pin is asserted low. Upon a
wake-up event, the SHDN pin is released (VDDBU level).
Zero-Power Power-On
Reset Cell output
22 - 42 kHz RC
Oscillator output
Fast RC
Oscillator output
Backup Power Supply
SHDN
Core Regulator Status
from BOD core
(vddcore_nreset)
NRST
(no ext. drive assumed)
Processor Reset
(Core 0 only)
Note: After processor reset rising, the core starts fetching instructions from Flash at 4 MHz.
Peripheral Reset
7 x Slow Clock Cycles
(5 for startup slow RC + 2 for synchro.)
3 x Slow Clock
Cycles
2 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
T
ON
Voltage
Regulator
Zero-Power POR
Core Power Supply
default = 2
System Reset