393
SAM4CP [DATASHEET]
43051E–ATPL–08/14
25.3
Product Dependencies
25.3.1 Power Management
The Interprocessor Communication module is not continuously clocked. The IPC interface is clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to enable the IPC clock.
25.3.2 Interrupt Line
The IPC module has an interrupt line connected to the Interrupt Controller. Handling interrupts requires programming the
Interrupt Controller before configuring the IPC.
25.4
Functional Description
25.4.1 Interrupt Sources
25.4.1.1 Interrupt Generation
Interrupt sources can be individually generated by writing respectively the IPC_ISCR and IPC_ICCR registers.
25.4.1.2 Interrupt Source Control
Each interrupt source (IRQ0 to IRQ31) can be enabled or disabled by using the command registers: IPC_IECR (Interrupt
Enable Command Register) and IPC_IDCR (Interrupt Disable Command Register). This set of registers conducts
enabling or disabling of an instruction. The interrupt mask can be read in the IPC_IMR register. All IPC interrupts can be
enabled/disabled, thus configuring the IPC Interrupt mask register. Each pending and unmasked IPC interrupt asserts
the IPC output interrupt line. A disabled interrupt does not affect servicing of other interrupts.
25.4.1.3 Interrupt Status
The IPC_IECR and IPC_IDCR registers are used to determine which interrupt sources are active/inhibited to generate an
interrupt output. The IPC_IMR register is a status of the interrupt source selection (a result from write into the IPC_IECR
and IPC_IDCR registers). The IPC_ISCR and IPC_ICCR registers are used to activate/inhibit interrupt sources. The
IPC_IPR register is a status register giving active interrupt sources.
The IPC_ISR register reports which interrupt source(s) is(are) currently asserting an interrupt output. IPC_ISR is
basically equivalent to an AND between the IPC_IPR and IPC_IMR registers.
Table 25-1.
Peripheral IDs
Instance
ID
IPC0
31
IPC1
39