592
SAM4CP [DATASHEET]
43051E–ATPL–08/14
32.5.14 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address spaces can be write-
protected by setting the WPEN bit in the
“PIO Write Protection Mode Register”
(PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
“PIO Write Protection Status Register”
(PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
“PIO Enable Register” on page 596
“PIO Disable Register” on page 597
“PIO Output Enable Register” on page 599
“PIO Output Disable Register” on page 600
“PIO Input Filter Enable Register” on page 602
“PIO Input Filter Disable Register” on page 603
“PIO Multi-driver Enable Register” on page 613
“PIO Multi-driver Disable Register” on page 614
“PIO Pull-Up Disable Register” on page 616
“PIO Pull-Up Enable Register” on page 617
“PIO Peripheral ABCD Select Register 1” on page 619
“PIO Peripheral ABCD Select Register 2” on page 620
“PIO Output Write Enable Register” on page 628
“PIO Output Write Disable Register” on page 629
“PIO Pad Pull-Down Disable Register” on page 625
“PIO Pad Pull-Down Status Register” on page 627
PIO_MDER
0x0000_000F
PIO_MDDR
0xFFFF_FFF0
PIO_PUDR
0xFFF0_00F0
PIO_PUER
0x000F_FF0F
PIO_PPDDR
0xFF0F_FFFF
PIO_PPDER
0x00F0_0000
PIO_ABCDSR1
0xF0F0_0000
PIO_ABCDSR2
0xFF00_0000
PIO_OWER
0x0000_000F
PIO_OWDR
0x0FFF_ FFF0
Table 32-2.
Programming Example