
779
SAM4CP [DATASHEET]
43051E–ATPL–08/14
36.7.5 USART Interrupt Enable Register
Name:
US_IER
Address:
0x40024008 (0), 0x40028008 (1), 0x4002C008 (2), 0x40030008 (3), 0x40034008 (4)
Access:
Write-only
For SPI specific configuration, see
“USART Interrupt Enable Register (SPI_MODE)” on page 780
.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
RXRDY: RXRDY Interrupt Enable
TXRDY: TXRDY Interrupt Enable
RXBRK: Receiver Break Interrupt Enable
ENDRX: End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
ENDTX: End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
OVRE: Overrun Error Interrupt Enable
FRAME: Framing Error Interrupt Enable
PARE: Parity Error Interrupt Enable
TIMEOUT: Time-out Interrupt Enable
TXEMPTY: TXEMPTY Interrupt Enable
ITER: Max number of Repetitions Reached Interrupt Enable
TXBUFE: Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
RXBUFF: Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
NACK: Non Acknowledge Interrupt Enable
CTSIC: Clear to Send Input Change Interrupt Enable
MANE: Manchester Error Interrupt Enable
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANE
23
–
22
–
21
–
20
–
19
18
–
17
–
16
–
CTSIC
15
–
14
–
13
12
11
10
9
8
NACK
RXBUFF
TXBUFE
ITER
TXEMPTY
TIMEOUT
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
RXBRK
TXRDY
RXRDY