參數(shù)資料
型號: EVAL-ADV7173EBZ
廠商: Analog Devices Inc
文件頁數(shù): 11/60頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADV7173
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: ADV7173
主要屬性: NTSC/PAL 數(shù)字視頻編碼器
次要屬性: I²C 接口
已供物品:
REV. B
ADV7172/ADV7173
–19–
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
320
Figure 28. Timing Mode 1 (PAL)
Mode 1: Master Option
HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7172/ADV7173 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when
HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-
trates the
HSYNC, BLANK, and FIELD for an odd-or-even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
Figure 29. Timing Mode 1 Odd/Even Field Transitions Master/Slave
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