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參數(shù)資料
型號： EVAL-ADV7173EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 41/60頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV7173
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7173
主要屬性： NTSC/PAL 數(shù)字視頻編碼器
次要屬性： I²C 接口
已供物品： 板
REV. B
ADV7172/ADV7173
–46–
APPENDIX 5
TELETEXT INSERTION
Time, tPD, is the time needed by the ADV7172/ADV7173 to interpolate input data on TTX and insert it onto the CVBS or Y out-
puts, such that it appears tSYNTTXOUT = 10.2
s after the leading edge of the horizontal signal. Time, TTXDEL, is the pipeline delay
time by the source that is gated by the TTXREQ signal in order to deliver TTX data.
With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct
position of 10.2
s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays.
The width of the TTXREQ signal must always be maintained such that it allows the insertion of 360 (in order to comply with the
Teletext Standard “PAL-WST”) teletext bits at a text data rate of 6.9375 Mbits/s. This is achieved by setting TC03–TC00 to “0.”
The insertion window is not open if the Teletext Enable (MR33) is set to “0.”
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27 MHz/4) = 6.75 MHz
(6.9375
× 106/6.75 × 106) = 1.027777
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7172/ADV7173
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
that can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the same way. Individual control of teletext lines is controlled by Teletext Setup Registers.
ADDRESS & DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
Figure 72. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
tPD
CVBS/Y
HSYNC
TTXREQ
TTXDATA
tSYNTTXOUT = 10.2 s
tPD = PIPELINE DELAY THROUGH ADV7172/ADV7173
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
tSYNTTXOUT
10.2 s
TTXDEL
TTXST
Figure 73. Teletext Functionality Diagram
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