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參數(shù)資料
| 型號(hào)： | EVAL-ADV7173EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/60頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADV7173 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7173 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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REV. B
ADV7172/ADV7173
–27–
MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 44 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)
These bits are used to set up the encoder mode. The ADV7172/
ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL M or PAL N standard video.
Luma Filter Select (MR02–MR04)
These bits specify which luma filter is to be selected. The
filter selection is made independent of whether PAL or
NTSC is selected.
Chroma Filter Select (MR05–MR07)
These bits select the chroma filter. A low-pass filter can be
selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, or 2 MHz), along with a choice of CIF or QCIF filters.
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 45 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR15–MR10)
MR15–MR10 bits can be used to power down the DACs. This
can be used to reduce the power consumption of the ADV7172/
ADV7173 if any of the DACs are not required in the application.
Low Power Mode Control (MR16)
This bit enables the lower power mode of the ADV7172/
ADV7173. This will reduce by approximately 50% the average
supply current consumed by each large DAC which is powered
on. For each DAC in low power mode, the relationship between
RSET1/VREF and the output current is unchanged by this (see
Appendix 8). This bit is only relevant to the larger DACs,
DACs A, B, and C. DACs D, E, and F are not affected by this
low power mode.
Reserved (MR17)
A Logic “0” must be written to this bit.
CHROMA FILTER SELECT
MR07 MR06
0
1.3MHz LOW-PASS FILTER
0
1
0.65MHz LOW-PASS FILTER
0
1
0
1.0MHz LOW-PASS FILTER
0
1
2.0MHz LOW-PASS FILTER
1
0
RESERVED
1
0
1
CIF
1
0
QCIF
1
RESERVED
MR05
MR01
MR00
MR07
MR02
MR03
MR05
MR06
MR04
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0
NTSC
0
1
PAL (B, D, G, H, I)
1
0
PAL (M)
1
PAL (N)
LUMA FILTER SELECT
MR04 MR03
0
LOW-PASS FILTER (NTSC)
0
1
LOW-PASS FILTER (PAL)
0
1
0
NOTCH FILTER (NTSC)
0
1
NOTCH FILTER (PAL)
1
0
EXTENDED MODE
1
0
1
CIF
1
0
QCIF
1
RESERVED
MR02
Figure 44. Mode Register 0 (MR0)
MR11
MR10
MR17
MR12
MR13
MR15
MR16
MR14
LOW POWER MODE
CONTROL
0
DISABLE
1
ENABLE
MR16
MR14
DAC A
DAC C CONTROL
MR15
MR17
ZERO SHOULD BE
WRITTEN TO
THIS BIT
0
POWER-DOWN
1
NORMAL
0
POWER-DOWN
1
NORMAL
DAC B
DAC C CONTROL
DAC C
DAC C CONTROL
MR13
0
POWER-DOWN
1
NORMAL
DAC E
DAC C CONTROL
MR11
0
POWER-DOWN
1
NORMAL
MR12
0
POWER-DOWN
1
NORMAL
DAC D
DAC C CONTROL
DAC F
DAC C CONTROL
MR10
0
POWER-DOWN
1
NORMAL
Figure 45. Mode Register 1 (MR1)
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