參數(shù)資料
型號： EVAL-ADV7173EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/60頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV7173
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7173
主要屬性： NTSC/PAL 數(shù)字視頻編碼器
次要屬性： I²C 接口
已供物品： 板
REV. B
ADV7172/ADV7173
–30–
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Mode Register 4 is a 8-bit wide register. Figure 48 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H (MR40)
When this bit is enabled (“1”) in slave mode, it is possible to
drive the
VSYNC active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7172/ADV7173 outputs an active low
VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Selection (MR42–MR41)
These bits control the genlock feature of the ADV7172/ADV7173.
Setting MR41 to Logic “0” disables the SCRESET/RTC pin
and allows the ADV7172/ADV7173 to operate in normal mode.
By setting MR41 to “1,” one of two operations may be enabled:
1. If MR42 is set to “0,” the SCRESET/RTC pin is configured
as a subcarrier reset input and the subcarrier phase will reset
to Field 0 whenever a low-to-high field transition is detected
on the SCRESET/RTC pin.
2. If MR42 is set to “1,” the SCRESET/RTC pin is configured
as a real-time control input and the ADV7172/ADV7173 can
be used to lock to an external video source.
Active Video Line Duration (MR43)
This bit switches between two active video line durations. A
“0” selects CCIR REC 601 (720 pixels PAL/NTSC) and a “1”
selects ITU-R.BT 470 “analog” standard for active video dura-
tion (710 pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR45)
This bit enables the color burst information to be switched on
and off the video output.
Color Bar Control (MR46)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled, the ADV7172/ADV7173 is config-
ured in a master timing mode. The output pins
VSYNC/FIELD,
HSYNC and BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to set up the output to interlaced or noninter-
laced mode.
MR41
MR40
MR47
MR42
MR44
MR43
MR45
MR46
CHROMINANCE
CONTROL
0
ENABLE COLOR
1
DISABLE COLOR
MR44
COLOR BAR
CONTROL
0
DISABLE
1
ENABLE
MR46
VSYNC 3H
0
DISABLE
1
ENABLE
MR40
INTERLACED
MODE CONTROL
0
INTERLACED
1
NONINTERLACED
MR47
BURST
CONTROL
0
ENABLE BURST
1
DISABLE BURST
MR45
ACTIVE VIDEO
LINE DURATION
0
720 PIXELS
1
710/702 PIXELS
MR43
GENLOCK SELECTION
x
0
DISABLE GENLOCK
0
1
ENABLE SUBCARRIER
RESET PIN
1
ENABLE RTC PIN
MR42 MR41
Figure 48. Mode Register 4 (MR4)
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