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參數資料
| 型號： | EVAL-ADV7173EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 2/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADV7173 |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7173 |
| 主要屬性： | NTSC/PAL 數字視頻編碼器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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REV. B
ADV7172/ADV7173
–10–
PIN FUNCTION DESCRIPTION
Mnemonic
Input/Output
Function
P7–P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) P0 represents the LSB.
CLOCK
I
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alter-
natively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or as an input and accept (Slave Mode) Sync signals.
FIELD/
VSYNC
I/O
Dual Function FIELD (Mode 1) and
VSYNC (Mode 2) Control Signal. This pin may be
configured to output (Master Mode) or as an input (Slave Mode) and accept these
control signals.
BLANK
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level “0.”
This signal is optional.
SCRESET/RTC
I
This pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It
can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a Real-
Time Control (RTC) Input.
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
RSET1
I
A 150
resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs A, B, and C (the “l(fā)arge” DACs).
RSET2
I
A 600
resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs D, E, and F (the “small” DACs).
COMP1
O
Compensation Pin for DACs A, B, and C. Connect a 0.1
F Capacitor from COMP to
VAA. For Optimum Dynamic Performance in Low Power Mode, the value of the
COMP1 capacitor can be lowered to as low as 2.2 nF.
COMP2
O
Compensation Pin for DACs D, E, and F. Connect a 0.1
F Capacitor from COMP to V
AA.
DAC A
O
GREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.
DAC B
O
BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.
DAC C
O
RED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output.
DAC D
O
GREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.
DAC E
O
BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.
DAC F
O
RED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.
SCLOCK
I
MPU Port Serial Interface Clock Input.
SDATA
I/O
MPU Port Serial Data Input/Output.
CLAMP
O
TTL Output Signal to external circuitry to enable clamping of all video signals.
PAL_NTSC
I
Input signal to select PAL or NTSC mode of operation, pin set to Logic “1” selects PAL.
VSO
O
VSO TTL Output Sync Signal.
CSO_HSO
O
Dual Function
CSO or HSO TTL Output Sync Signal.
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
RESET
I
The input resets the on-chip timing generator and sets the ADV7172/ADV7173 into
default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered
OFF, DACs D, E, and F powered ON, Composite and S-Video out.
TTX
I
Teletext Data Input Pin.
TTXREQ
O
Teletext Data Request output signal used to control teletext data transfer.
VAA
P
Power Supply (3 V to 5 V).
GND
G
Ground Pin.
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