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| 型號： | EVAL-ADV7173EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/60頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADV7173 |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7173 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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REV. B
ADV7172/ADV7173
–31–
MODE REGISTER 5 MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 49 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the Y output level on the ADV7172/ADV7173.
If this bit is set (“0”), the encoder outputs SMPTE levels when
configured in PAL mode and Betacam levels when configured
in NTSC mode. If this bit is set (“1”), the encoder outputs
Betacam levels when configured in PAL mode and SMPTE
levels when configured in NTSC mode.
UV-Levels Control (MR52–MR51)
These bits control the U and V output levels on the ADV7172/
ADV7173. It is possible to have UV levels with a peak-peak
amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV
(MR52 + MR51 = “10”) in NTSC and PAL. It is also possible
to have default values of 934 mV for NTSC and 700 mV for
PAL (MR52 + MR51 = “00”).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR55–MR54)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7172/ADV7173. It is possible
to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP
signal. If this bit is set (“1”), the delay is negative. If it is not set
(“0”), the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (“1”), the CLAMP signal is located in the back porch posi-
tion. If this bit is set to (“0”), the CLAMP signal is located in
the front porch position.
MR51
MR50
MR57
MR52
MR54
MR53
MR55
MR56
CLAMP DELAY
DIRECTION
0
POSITIVE
1
NEGATIVE
MR56
CLAMP POSITION
0
FRONT PORCH
1
BACK PORCH
MR57
CLAMP DELAY
0
NO DELAY
01
1
PCLK
10
2
PCLK
11
3
PCLK
MR55 MR54
UV-LEVELS CONTROL
0
DEFAULT LEVELS
0
1
700mV
1
0
1000mV
1
RESERVED
MR52 MR51
RGB
SYNC
0
DISABLE
1
ENABLE
MR53
Y-LEVEL
CONTROL
0
DISABLE
1
ENABLE
MR50
Figure 49. Mode Register 5 (MR5)
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