參數(shù)資料
型號(hào)： EVAL-ADV7173EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/60頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV7173
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7173
主要屬性： NTSC/PAL 數(shù)字視頻編碼器
次要屬性： I²C 接口
已供物品： 板
REV. B
ADV7172/ADV7173
–37–
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07–TC00)
(Address (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure 59.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles.
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext Bits
below the default of 360. If Bits TC03–TC00 are 00Hex when
Bits TC07–TC04 are changed, then the falling edge of TTXREQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address (SR4–SR0) = 19H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60
shows the operations under control of this register.
C/W BIT DESCRIPTION
CGMS Data (C/W03–C/W00)
These four data bits are the final four bits of CGMS data out-
put stream. Note it is CGMS data ONLY in these bit positions
i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, are calculated internally by
the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note that this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note that this is only valid in NTSC mode.
Wide Screen Signal Control (C/W07)
When this bit is set (“1”), wide screen signalling is enabled.
Note that this is only valid in PAL mode.
TC01
TC00
TC07
TC02
TC04
TC03
TC05
TC06
TTXREQ RISING EDGE CONTROL
TC07 TC06
TC05 TC04
0
0 PCLK
0
1
1 PCLK
"
" PCLK
1
0
14 PCLK
1
15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02
TC01 TC00
0
0 PCLK
0
1
1 PCLK
"
" PCLK
1
0
14 PCLK
1
15 PCLK
Figure 59. Teletext Request Control Register
CGMS CRC CHECK
CONTROL
0
DISABLE
1
ENABLE
C/W04
WIDE SCREEN SIGNAL
CONTROL
0
DISABLE
1
ENABLE
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
CGMS ODD FIELD
CONTROL
0
DISABLE
1
ENABLE
C/W05
C/W03–C/W00
CGMS DATA
CGMS EVEN FIELD
CONTROL
0
DISABLE
1
ENABLE
C/W06
Figure 60. CGMS_WSS Register 0
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