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| 型號： | EVAL-ADV7173EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADV7173 |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7173 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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REV. B
ADV7172/ADV7173
–24–
CSO, HSO, AND VSO OUTPUTS
The ADV7172/ADV7173 supports three timing signals,
CSO
(composite sync signal),
HSO (horizontal sync signal) and VSO
(vertical sync signal). These output TTL signals are aligned with
the analog video outputs.
HSO and CSO are shared on Pin 10.
Mode Register 7, Bit MR75 can be used to configure this out-
put pin. See Figure 37 for an example of these waveforms.
CLAMP OUTPUT
The ADV7172/ADV7173 has a programmable clamp TTL
output signal. The clamp signal is programmable to the front
and back porch. Mode Register 5, Bit MR57 can be used to
control the porch position. Also the position of the clamp signal
can be varied by 1–3 clock cycles in a positive and negative
direction from the default position. Mode Register 5, Bits MR56,
MR55, and MR54 control this position.
MR57 = 1
MR57 = 0
0H
Figure 38. Clamp Output Timing
MPU PORT DESCRIPTION
The ADV7172 and ADV7173 support a 2-wire serial (I
2C-
Compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7172 and ADV7173 each have four possible slave addresses
for both read and write operations. These are unique addresses
for each device and are illustrated in Figure 39 and Figure 40.
The LSB sets either a read or write operation. Logic Level
“1” corresponds to a read operation while Logic Level “0”
corresponds to a write operation. A1 is set by setting the ALSB
pin of the ADV7172/ADV7173 to Logic Level “0” or Logic
Level “1.” When ALSB is set to “0,” there is greater bandwidth
on the I
2C lines, which allows high-speed data transfers on this
bus. When ALSB is set to “1,” there is reduced input band-
width on the I
2C lines, which means that impulses of less
than 50 ns will not pass into the I
2C internal controller. This
mode is recommended for noisy systems.
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
WRITE
1
READ
1
0
1
0
1
A1
X
Figure 39. ADV7172 Slave Address
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
WRITE
1
READ
0
1
0
1
0
1
A1
X
Figure 40. ADV7173 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the Start condition and shift the next eight bits (7-bit address +
R/
W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/
W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
VSO
HSO
CSO
OUTPUT
VIDEO
525
123456789
10
11-19
EXAMPLE: NTSC
Figure 37.
CSO, HSO, VSO Timing Diagram
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