- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16530 > EVAL-ADV7173EBZ (Analog Devices Inc)BOARD EVALUATION FOR ADV7173 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADV7173EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADV7173 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7173 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
REV. B
ADV7172/ADV7173
–41–
The ADV7172/ADV7173 is a highly integrated circuit containing
both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be applied
to the system level design so that high speed, accurate performance
is achieved. The Recommended Analog Circuit Layout shows
the analog interface between the device and monitor.
The layout should be optimized for lowest noise on the ADV7172/
ADV7173 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of VAA and GND pins should by minimized to minimize induc-
tive ringing.
Ground Planes
The ground plane should encompass all ADV7172/ADV7173
ground pins, voltage reference circuitry, power supply bypass cir-
cuitry for the ADV7172/ADV7173, the analog output traces, and
all the digital signal traces leading up to the ADV7172/ADV7173.
The ground plane is the board’s common ground plane.
Power Planes
The ADV7172/ADV7173, and any associated analog circuitry,
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7172/ADV7173.
The metallization gap separating device power plane and
board power plane should be as narrow as possible to mini-
mize the obstruction to the flow of heat from the device into
the general board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7172/ADV7173 power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
Supply Decoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
obtained with 0.1
F ceramic capacitor decoupling. Each group
of VAA pins on the ADV7172/ADV7173 must have at least one
0.1
F decoupling capacitor to GND. These capacitors should
be placed as close to the device as possible.
It is important to note that while the ADV7172/ADV7173
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three-terminal voltage
regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7172/ADV7173 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7172/ADV7173 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
Analog Signal Interconnect
The ADV7172/ADV7173 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75
load
resistor connected to GND. These resistors should be placed
as close as possible to the ADV7172/ADV7173 to minimize
reflections.
The ADV7172/ADV7173 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCP121T-450E/TT | IC SUPERVISOR 4.38V LOW S0T-23B |
| VE-J0H-EZ-S | CONVERTER MOD DC/DC 52V 25W |
| M3TTK-1036R | IDC CABLE - MSD10K/MC10M/MSD10K |
| UVR1V331MPD1TD | CAP ALUM 330UF 35V 20% RADIAL |
| ECC13DRXS-S734 | CONN EDGECARD 26POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV7174EBM | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| EVAL-ADV7179EBM | 制造商:Analog Devices 功能描述:EVALUATION BOARD IC - Bulk |
| EVAL-ADV7179EBZ | 功能描述:BOARD EVALUATION FOR ADV7179 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADV7180-32EBZ | 功能描述:BOARD EVAL FOR ADV7180 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADV7180-48EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 4?? Oversampling SDTV Video Decoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。