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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 14/34頁 |
| 文件大小： | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 14 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
3.1
PIN DESCRIPTIONS
SIGNAL
DESCRIPTION
DI[0:11]
INPUT DATA.
Active high
The 12 bit two’s complement input samples. New samples are
clocked into the chip on the rising edge of the clock. The input data
rate is assumed to be equal to the clock rate.
CK
INPUT CLOCK.
Active high
The clock input to the chip. The input signals are clocked into the
chip on the rising edge of this clock.
OCK
OUTPUT CLOCK.
Active high
The output signals are clocked out of the chip on the rising edge
of this clock.
SI
SYNC IN
. Active low
The sync input to the chip. All timers, accumulators, and control
counters are, or can be, synchronized to
SI
. This sync is clocked
into the chip on the rising edge of the input clock (
CK
).
EIN
ERROR IN
. Active high
The external error input to the rate-lock-loop circuit. This signal is
sampled on the rising edge of the input clock (
CK
).
EVAL
ERROR VALID
. Active high
EVAL
identifies when the error to the RLL is valid. The
rate-lock-loop circuit updates when
EVAL
is high. This signal is
sampled on the rising edge of the input clock (
CK
).
DO[0:11]
OUTPUT DATA
. Active high
The resampled data are output as a 12 bit words on these pins.
The bits are clocked out on the rising edge of the output clock
(
OCK
).
DVAL
DATA VALID
. Programmable active high or low level
The data valid strobe. This strobe is used to identify the valid
output samples when the chip is operated in the synchronous I/O
mode (common I/O clock mode). This strobe is clocked out of the
chip on the rising edge of the clock (
CK
). This strobe is active for
the clock cycle just before
DO
changes. The high/low polarity of
the strobe is programmable. See Section 2.5 for details.
SO
SYNC OUT
. Active low
This signal is either a delayed version of the input sync
SI
, the
sync counter’s terminal count (TC), or a one-shot strobe. The
SO
signal is clocked out of the chip on the rising edge of the output
clock (
OCK
).
M/S
MASTER/SLAVE CONTROL
. High for master, low for slave
This pin determines if the chip is the master or slave in a multi-chip
synchronization mode. This pin should be pulled high for the
master chip and grounded for the slave chips.
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