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| 型號(hào)： | GC3011-CQ |
| 文件頁數(shù)： | 21/34頁 |
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| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 21 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
4.4
SYNC MODE REGISTER
The Sync mode control register determines how the circuits within the chip are synchronized. Each
circuit which requires synchronization can be configured to be synchronized to the sync input
(SI
), or to the
terminal count of the sync counter (
TC
). The sync to each circuit can also be set to be always on or always
off. Each circuit is given a two bit sync mode control which is defined as:
NOTE: the internal syncs are active high. The
SI
input has been inverted to be the active high sync
SI
.
ADDRESS 8:
SYNC MODE
BIT
TYPE
NAME
DESCRIPTION
0,1 (LSBs)
2,3
R/W
R/W
LOAD_RATIO
RATE_ACC
The resampling ratio load selection
The rate accumulator sync selection. The rate
accumulator in the RLL is initialized when this sync
occurs.
The delay accumulator sync selection. The delay
accumulator is initialized when this sync occurs.
The selected sync is inverted and output on the
SO
pin.
Mode 0 in Table 1 is replaced by the one-shot sync for
the output sync selection.
4,5
R/W
DELAY_ACC
6,7
R/W
OUTPUT_SYNC
Table 2: SYNC MODES
MODE
SYNC DESCRIPTION
0
“0” (never asserted)
1
SI
2
TC
3
“1” (always)
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