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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 7 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
Output samples are clocked into the FIFO by the interpolation control circuit at a rate determined
by the interpolation ratio. For example, if the interpolation ratio is set at 1.5, then two samples will be clocked
into the FIFO for every 3 input clocks. If the ratio is 2.25, then four samples would be stored in the FIFO for
every nine input clocks. The FIFO timing for a ratio of 1.5 is shown in Figure 4.
Figure 4. Fifo Timing
2.7.1
FIFO ERRORS
Notice that the output data samples in Figure 4 are delayed by 8 clock cycles relative to the input
samples. This is the ideal case when the FIFO is half full. If the output clock is faster than the FIFO input
clock, then the FIFO will empty and an underflow error will occur. If the output clock is slower than the FIFO
input clock, then the FIFO will fill up and an overflow error will occur. The FIFO will remain in the overflow
or underflow condition until the I/O rates change and the FIFO begins to empty or fill, or until the FIFO is
reset. The output samples will not be valid when an underflow/overflow error occurs.
The FIFO generates half full and FIFO error flags. The half full flag is high whenever the FIFO
contains more than 8 samples. The FIFO error flag is high whenever the FIFO contains less than 2 or more
than 14 samples. The FIFO half full and error flags are output from the chip on the HF and FE pins. The
user can also monitor the FIFO using the HALF_FULL, FIFO_FULL, FIFO_EMPTY and FIFO_DEPTH
control bits in the FIFO control register (see Sections 4.8 and 4.9). The FIFO_FULL and FIFO_EMPTY
control bits are set when an overflow or underflow condition occurs and will remain set until the user clears
the bits. The FIFO_DEPTH is a read only 4 bit field which reflects the depth of the FIFO. The depth is
encoded as a 4 bit gray scale number to minimize errors when reading the FIFO depth. The mapping
between grayscale and binary is as follows:
FIFO_EMPTY
HALF_FULL
FIFO_FULL
GRAY SCALE:
0 1 3 2 6 7 5 4 C D F E A B 9 8
HEX:
0 1 2 3 4 5 6 7 8 9 A B C D E F
INPUT CLOCK
FIFO INPUT
(FROM FILTER)
FIFO INPUT
CLOCK
VALID FLAG
Y9
Y10
Y11
Y12
Y13
Y14
FIFO OUTPUT
CLOCK
FIFO OUTPUT
(TO DOUT)
Y0
Y15
Y1
Y2
Y3
Y4
Y5
Y6
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