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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 4/34頁 |
| 文件大?。?/td> | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 4 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
2.5
INTERPOLATION RLL
The interpolation ratio can be fixed by the user, or can be allowed to adapt to the ratio that keeps
the output FIFO half-full. The adaption is performed by the interpolation rate lock loop (RLL) circuit. Figure
2 is a block diagram showing the interpolation RLL circuit and the interpolation control circuit.
Figure 2. Interpolation RLL And Control Circuits
2.5.1
Fixed Interpolation Mode
The fixed interpolation mode is used when the user knows what the desired output rate should be
relative to the input rate. For example, a user may wish to use this mode when he is using the resampler to
baud synchronize a modem signal. In this case the user has an external baud rate detection circuit which
tells the user how to adjust the interpolation ratio.
The user fixes the interpolation ratio by turning off (clearing) the Rate-Locked-Loop (RLL) circuit.
Clearing the RLL output fixes the delay accumulator’s input to be the 32 bit value supplied by the user.
2.5.2
Adaptive Interpolation Mode
In this mode the RLL circuit automatically adjusts the interpolation ratio to keep the FIFO half full.
This mode is used when the output clock is fixed and the chip’s interpolation ratio must exactly match the
ratio between the chip’s input clock and the output clock. For example, a user may wish to use the adaptive
interpolation mode in order to interface two asynchronous signal processing systems, or when an external
baud sync circuit has provided a baud synchronous output clock.
The adaption uses an error signal from the FIFO. The error is a bit indicating the error is plus or
minus one. A minus one indicates that the FIFO is less than half full and the interpolation ratio (the ratio of
the input rate to the output rate) needs to be decreased. A plus one indicates that the FIFO is more than
half full and the interpolation ratio needs to be increased. The user sets up the adaptive interpolation mode
2
-A
OR CLEAR
2
-B
OR CLEAR
ERROR
FROM
FIFO
RATE-LOCKED-LOOP
INTERPOLATION
RATIO
DELAY
CONTROL
WORD
(12 BITS)
CLEAR
DELAY ACCUMULATOR
32 bits
32 bits
RATIO_HOLD
TO
CONTROL
INTERFACE
16 MSBs
32 bits
INTERPOLATION CONTROL
M
EXT_ERR
EIN
EVAL
ERROR
LATCH
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