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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 24/34頁 |
| 文件大小： | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 24 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
4.7
CLOCK MODE REGISTERS
The clock mode registers control the phase-lock-loop (PLL) and voltage controlled oscillator (VCO)
in the output clock generator. NOTE: This register presets to 60 (HEX) upon power up.
ADDRESS 11:
Clock Mode register 0
BIT
TYPE
NAME
DESCRIPTION
0-3
R/W
RING_LENGTH
This four bit value, if the FORCE_LENGTH bit is
set, sets the length of the inverter chain used in the
VCO. The longer the chain, the slower the VCO
frequency.
This four bit value, if the FORCE_DIVIDE bit is set,
sets the power-of-two divide of the VCO output. The
larger the divide, the slower the clock output.
4-7
R/W
RING_DIVIDE
ADDRESS 12:
Clock Mode register 1
BIT
TYPE
NAME
DESCRIPTION
0
R/W
EXTENDED_RANGE
This bit puts the VCO in the extended PLL range
mode. This doubles the pull range of the VCO at the
expense of some additional clock jitter.
This bit forces the length of the VCO inverter chain
to RING_LENGTH.
This bit forces the divide of the VCO output to
RING_DIVIDE.
This bit puts the ring oscillator in a test mode by
breaking the ring of inverters and using the OCK
clock input as the first stage of the oscillator.
This bit shortens the divider from 16 stages to 8
stages for test purposes.
This bit forces the PLL to be in the reset state ready
for a new acquisition cycle. In the reset state the
VCO control voltage is forced to its middle setting,
the ring divider (FORCE_DIVIDE must be off) is
forced to maximum, and the ring length
(FORCE_LENGTH must be off) is set to 8. The PLL
will adapt to the resampler’s output data rate when
PLL_RESET is cleared and VCO_ENABLE is set.
This bit turns on the VCO. The output clock is
cleared when this bit is low.
Turns on the 2X clock output.
1
R/W
FORCE_LENGTH
2
R/W
FORCE_DIVIDE
3
R/W
VCO_TEST
4
R/W
DIVIDE_TEST
5
R/W
PLL_RESET
6
R/W
VCO_ENABLE
7
R/W
CK2X_ENABLE
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