參數(shù)資料
型號(hào)： GC3011-CQ
文件頁(yè)數(shù)： 8/34頁(yè)
文件大?。?/td> 194K
代理商： GC3011-CQ
GRAYCHIP,INC.
- 8 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
2.7.2
FIFO RESET
The FIFO is initialized to its half full state by setting the FRST pin high or by using the FIFO_RESET
control mode (See Section 4.6). The FIFO will remain in the half full state until the FRST pin is set low. The
8 outputs following a FIFO_RESET will be invalid.
2.8
OUTPUT CLOCK GENERATOR
The resampled data can be output either synchronous to the input clock, synchronous to an
internally generated output clock, or synchronous to an externally provided output clock. A separate clock
input pin (OCK) is provided for the output data clock. The user connects this clock pin to either the input
clock, the internally generated resampled clock (CKOUT), or to an externally provided clock as described
below.
2.8.1
Synchronous Output Mode
In this mode the output FIFO is bypassed and the data is output synchronous to the input clock. The
samples are accompanied by a data valid strobe (DVAL) which indicates whether the user should skip or
accept each output sample. The polarity of the strobe can be programmed as active high or low depending
upon how the user wants to use it. A typical use of the DVAL strobe would be as an enable strobe to external
registers or FIFOs. In the DVAL_EARLY mode (See Section 4.6) the DVAL signal is active one clock cycle
early so that it can be used as a clock enable to the GC2011 or GC3021 chips which expect the clock enable
to arrive one clock earlier than the data.
In the synchronous output mode the input clock pin (CK) must be tied to the output clock pin (OCK).
2.8.2
Internally Generated Clock
A voltage controlled oscillator (VCO) and charge-pump phase-lock-loop (PLL)
1
is built into the
GC3011 to generate a smooth clock to match the resampled data rate. The VCO consists of a odd number
of inverters connected in a ring (commonly known as a ring oscillator). The clock frequency is controlled by
dividing the ring oscillator output by a factor of 2
n
, by varying the number of stages in the ring and by
adjusting a control voltage. The output of the ring oscillator can be divided by 2
n
where n ranges from 0 to
15. The number of stages in the ring oscillator can be varied digitally from 1 to 16. Each stage is
non-inverting, a final stage provides the feedback inversion. The control voltage adjusts the delay of each
stage and hence the frequency of oscillation. The control voltage can adjust the oscillation frequency in
either a narrow range adjust mode or wide range adjust mode. In the narrow mode the control voltage can
adjust the frequency by
±
12%. These parameters allow the output clock to be generated with a minimum
frequency of 10 KHz and a maximum frequency of 80 MHz.
1. F. M. Gardner, “Charge-Pump Phase-Lock-Loops”, IEEE Transactions on Communications, vol. COM-28, pp.
1849-1858, Nov. 1980
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