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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 23/34頁 |
| 文件大?。?/td> | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 23 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
4.6
OUTPUT MODE REGISTER
These register sets various output mode controls.
ADDRESS 10:
Output Mode Register
BIT
TYPE
NAME
DESCRIPTION
0-1
R/W
FIFO_RESET
The FIFO is reset to half full according to Table 1 in
Section 4.4.
Turns off the FIFO so that the data and the data
valid flag bypass the FIFO and are output directly
from the chip. The OCK pin must be tied to the CK
pin in this mode.
2
R/W
BYPASS
3
4
R/W
R/W
Unused
DVAL_EARLY
Normally the DVAL is active for the clock cycle just
before the DO output changes. When this bit is set
the DVAL strobe comes out one clock earlier so that
it can be used as a clock enable to GRAYCHIP
devices which need the clock enable to be active
one clock earlier.
The DVAL strobe is normally active high. DVAL is
active low when DVAL_POL is high.
Used to turn off FIFO multi-chip synch signals
during diagnostics.
The FIFO driven phase detector is turned off when
this bit is set and the PLL is driven by the phase
detector only. Normally low.
5
R/W
DVAL_POL
6
R/W
FTEST
7
R/W
PHASE_ONLY
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