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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 25/34頁 |
| 文件大小： | 194K |
| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 25 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
4.8
STATUS CONTROL REGISTER
This register contains miscellaneous control and status information.
ADDRESS 13:
Status Control Register
BIT
TYPE
NAME
DESCRIPTION
0,1
R/W
STATUS_SELECT
Sets the mode of the STATUS registers as follows:
STATUS_SELECT
0
1
2
3
The ratio register tracks the value of the resampler
ratio when this bit is low and holds the last value
when this bit is high.
This
control
bit
turns
synchronization logic.
Use the external error signals EIN and EVAL
instead of the FIFO error to update the
rate-lock-loop.
A one-shot strobe is generated each time this bit is
set high. The bit must be cleared before another
one-shot strobe can be generated.
This two bit field controls the power down and keep
alive circuit as follows:
POWER_DOWN
0
1
2
3
The power_down bits default to 0 (clock loss detect
mode) upon power up.
MODE
Read ratio
Read FIFO status
Read PLL status
Read checksum
2
R/W
RATIO_HOLD
3
R/W
MULTI_MODE
on
the
multi-chip
4
R/W
EXT_ERR_MODE
5
R/W
ONE_SHOT
6,7
R/W
POWER_DOWN
MODE
Clock loss detect mode
Power down mode
Disabled
Test
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