參數(shù)資料
型號(hào)： GC3011-CQ
文件頁(yè)數(shù)： 31/34頁(yè)
文件大?。?/td> 194K
代理商： GC3011-CQ
GRAYCHIP,INC.
- 31 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
6.5
SYNCHRONIZING MULTIPLE GC3011 CHIPS
A system containing two or more GC3011 chips will need to be synchronized so that their
resampling delays and output FIFOs are locked. This is done using the multi-chip synchronization signals
DC[0:11], CV, FOZ, FIZ and M/S as described in Section 2.6. A block diagram showing how to configure
the chips is shown in Figure 6.
.
Figure 6. SYNCHRONIZING MULTIPLE GC3011 CHIPS
Figure 6 shows how one would configure the chips to resample complex data. The sync input is not
necessary unless there are system wide diagnostics which require it.
DI
DC
I
IN
DV FOZ
FIZ
SI
CK
OCK
CKOUT
M/S
DO
I
OUT
DI
Q
IN
SI
CK
OCK
CKOUT
M/S
DO
Q
OUT
CLOCK
DRIVER
CHIP
GC3011
“SLAVE”
GC3011
“MASTER”
SYNC IN
INPUT
CLOCK
OUTPUT
CLOCK
DC
DV FOZ
FIZ
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