參數(shù)資料
型號(hào)： KM48S8030B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 8Bit x 4 Banks Synchronous DRAM(2M x 8位 x 4組同步動(dòng)態(tài)RAM)
中文描述： 200萬(wàn)× 8位× 4銀行同步DRAM（2米× 8位× 4組同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 23/43頁(yè)
文件大?。?/td> 625K
代理商： KM48S8030B
CMOS SDRAM
DEVICE OPERATIONS - III
ELECTRONICS
REV. 3 Feb. '98
12. About Burst Type Control
At MRS A
3
= "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
At MRS A
3
= "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Basic
MODE
Random
MODE
Sequential Counting
Interleave Counting
Random column Access
t
CCD
= 1 CLK
13. About Burst Length Control
At MRS A
2,1,0
= "000".
At auto precharge, t
RAS
should not be violated.
At MRS A
2,1,0
= "001".
At auto precharge, t
RAS
should not be violated.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t
RDL
= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Basic
MODE
Interrupt
MODE
1
2
RAS Interrupt
(Interrupted by Precharge)
At MRS A
2,1,0
= "010".
At MRS A
2,1,0
= "011".
At MRS A
2,1,0
= "111".
At the end of the burst length, burst will be stop automatically.
At MRS A
9
= "1".
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, t
RAS
should not be violated.
t
BDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
4
8
Full Page
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
BRSW
Burst Stop
CAS Interrupt
Random
MODE
Special
MODE
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