參數(shù)資料
型號(hào)： KM48S8030B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 8Bit x 4 Banks Synchronous DRAM(2M x 8位 x 4組同步動(dòng)態(tài)RAM)
中文描述： 200萬× 8位× 4銀行同步DRAM（2米× 8位× 4組同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 42/43頁(yè)
文件大?。?/td> 625K
代理商： KM48S8030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ó
ELECTRONICS
REV. 2 Mar. '98
Self Refresh Entry & Exit Cycle
Self Refresh Entry
: Don't care
*Note :
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays
cf.) Once the device enters self refresh mode, minimum t
"Low".
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst ref
resh.
*Note 1
*Note 7
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
Hi-Z
ó
ó
ó
ó
ó
ó
Hi-Z
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
Self Refresh Exit
Auto Refresh
tSS
*Note 2
*Note 3
*Note 4
tRCmin
*Note 6
*Note 5
BA
0
~BA
1
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
ó
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
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KM48S8030C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit x 4 Banks Synchronous DRAM
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