參數(shù)資料
型號(hào): KM48S8030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 8Bit x 4 Banks Synchronous DRAM(2M x 8位 x 4組同步動(dòng)態(tài)RAM)
中文描述: 200萬(wàn)× 8位× 4銀行同步DRAM(2米× 8位× 4組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 43/43頁(yè)
文件大小: 625K
代理商: KM48S8030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 7 8 9 10
ELECTRONICS
REV. 2 Mar. '98
Mode Register Set Cycle
HIGH
MRS
Auto Refresh
: Don't care
*Note :
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
New
Command
New Command
Hi-Z
Hi-Z
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
tRC
ó
ó
HIGH
MODE REGISTER SET CYCLE
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
Auto Refresh Cycle
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Key
Ra
*Note 3
*Note 1
*Note 2
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