參數(shù)資料
型號(hào)： M58MR016C
廠商： 意法半導(dǎo)體
英文描述： 16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 16兆1兆x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 13/51頁
文件大小： 389K
代理商： M58MR016C
13/51
M58MR016C, M58MR016D
CFI Query (RCFI)
The CFI Query Mode is associated to bank A. The
address of the first write cycle must be within the
bank A. The status of the other bank is not affected
by the command (see Table 8). Writing 98h the de-
vice enters the Common Flash Interface Query
mode. Next read operations in the bank A will read
the CFI data. Write a read instruction to return to
Read mode (refer to the Common Flash Interface
section).
Clear Status Register (CLSR)
The Clear Status Register uses a single write op-
eration, which resets bits b1, b3, b4 e b5 of the sta-
tus register. The Clear Status Register is executed
writing the command 50h independently of the ap-
plied V
PP
voltage. After executing this command
the device returns to read array mode. The Clear
Status Register command clears only the status
register of the addressed bank.
Block Erase (EE)
Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to pre-program the block as the
P/E.C. will do it automatically before erasing. This
instruction use two writes cycles. The first com-
mand written is the Block Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased should be given to the memory during the
two cycles command. If the second command giv-
en is not an erase confirm, the status register bits
b4 and b5 are set and the instruction aborts.
After writing the command, the device outputs sta-
tus register data when any address within the bank
is read. At the end of the operation the bank will re-
main in read status register until a read array com-
mand is written.
Status Register bit b7 is ’0’ while the erasure is in
progress and ’1’ when it has completed. After com-
pletion the Status Register bit b5 returns ’1’ if there
has been an Erase Failure. Status register bit b1
returns ’1’ if the user is attempting to erase a pro-
tected block. Status Register bit b3 returns a ’1’ if
V
PP
is below V
PPLK
. Erase aborts if RP turns to
V
IL
. As data integrity cannot be guaranteed when
the erase operation is aborted, the erase must be
repeated (see Table 12). A Clear Status Register
instruction must be issued to reset b1, b3, b4 and
b5 of the Status Register. During the execution of
the erase by the P/E.C., the bank with the block in
erase accepts only the RSR (Read Status Regis-
ter) and PES (Program/Erase Suspend) instruc-
tions. See figure 19 for Erase Flowchart and
Pseudo Code.
Bank Erase (BE)
Bank erase sets all the bits within the selected
bank to ’1’. It is not necessary to pre-program the
block as the P/E.C. will do it automatically before
erasing.
This instruction uses two writes cycles. The first
command written is the Bank Erase set-up com-
mand 80h. The second command is the Erase
Confirm command D0h. An address within the
bank to be erased should be given to the memory
during the two cycles command. See the Block
Erase command section for status register bit de-
tails.
Program (PG)
The Program instruction programs the array on a
word-by-word basis. The first command must be
given to the target block and only one partition can
be programmed at a time; the other partition must
be in one of the read modes or in the erase sus-
pended mode (see Table 8).
This instruction uses two write cycles. The first
command written is the Program Set-up command
40h (or 10h). A second write operation latches the
Address and the Data to be written and starts the
P/E.C.
Read operations in the targeted bank output the
Status Register content after the programming
has started.
The Status Register bit b7 returns '0' while the pro-
gramming is in progress and '1' when it has com-
pleted. After completion the Status register bit b4
returns '1' if there has been a Program Failure (see
Table 12). Status register bit b1 returns '1' if the
user is attempting to program a protected block.
Status Register bit b3 returns a '1' if V
PP
is below
V
PPLK
. Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set) if V
PP
= V
PPH
and will be ig-
nored if V
PP
= V
PP1
.
Programming aborts if RP goes to V
IL
. As data in-
tegrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed. A Clear Status Register instruction
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