參數(shù)資料
型號: M58MR016C
廠商: 意法半導(dǎo)體
英文描述: 16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 16兆1兆x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 17/51頁
文件大?。?/td> 389K
代理商: M58MR016C
17/51
M58MR016C, M58MR016D
duces active current consumption. Program is
aborted if RP turns to V
IL
.
If a Program Suspend instruction was previously
executed, the Program operation may be resumed
by issuing the command D0h using an address
within the suspended bank (see Table 11). The
status register bit b2 and bit b7 are cleared when
program resumes and read operations output the
status register after the erase is resumed (see Ta-
ble 12). The suggested flowchart for program sus-
pend/resume features of the memory is shown
from Figure 18.
Block Protect (BP)
The BP instruction use two write cycles. The first
command written is the protection set-up 60h. The
second command is block Protect command 01h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Unprotect (BU)
The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Unprotect command D0h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Lock (BL)
The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Lock command 2Fh,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands. To read the status register
write the RSR command (see Table 12).
BLOCK PROTECTION
The M58MR016C/M58MR016D provide a flexible
protection of all the memory providing the protec-
tion, un-protection and locking of any blocks. All
blocks are protected at power-up. Each block of
the array has two levels of protection against pro-
gramming or erasing operation. The first level is
set by the Block Protect instruction; a protected
block cannot be programmed or erased until a
Block Unprotect instruction is given for that block.
A second level of protection is set by the Block
Lock instruction, and requires the use of the WP
pin, according to the following scheme:
– when WP is at V
IH
, the Lock status is overridden
and all blocks can be protected or unprotected;
– when WP is at V
IL
, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status;
– the lock status is cleared for all blocks at power
up.
The protection and lock status can be monitored
for each block using the Read Electronic Signature
(RSIG) instruction. Protected blocks will output a
'1' on DQ0 and locked blocks will output a '1' in
DQ1 (see Table 13).
PROTECTION REGISTER PROGRAM (PRP)
and LOCK PROTECTION REGISTER
PROGRAM (LPRP)
The M58MR016C/M58MR016D features a 128-bit
protection register and a security Block in order to
increase the protection of a system design. The
Protection Register is divided in two 64-bit seg-
ments. The first segment (81h to 84h) is a unique
device number, while the second one (85h to 88h)
can be programmed by the user. When shipped
the user programmable segment is read at '1'. It
can be only programmed at '0'.
The user programmable segment can be protect-
ed writing the bit 1 of the Protection Lock register
(80h). The bit 1 protects also the bit 2 of the Pro-
tection Lock Register.
The M58MR016C/M58MR016D feature a security
Block. The security Block is located at 0FF000-
0FFFFF (M58MR016C) or at 000000-000FFF
(M58MR016D) of the device. This block can be
permanently protected by the user programming
the bit 2 of the Protection Lock Register (see Fig-
ure 5).
The protection Register and the Protection Lock
Register can be read using the RSIG and RCFI in-
structions. A subsequent read in the address start-
ing from 80h to 88h, the user will retrieve
respectively the Protection Lock register, the
unique device number segment and the OTP user
programmable register segment (see Table 23).
WRITE READ CONFIGURATION REGISTER
(CR).
This instruction uses two Coded Cycles, the first
write cycle is the write Read Configuration Regis-
ter set-up 60h, the second write cycle is write
Read Configuration Register confirm 03h both to
Read Configuration Register address (see Table
11).
This instruction writes the contents of address bits
ADQ15-ADQ0 to bits CR15-CR0 of the Read Con-
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