參數資料
型號: M58MR016C
廠商: 意法半導體
英文描述: 16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 16兆1兆x16插槽,復用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數: 20/51頁
文件大?。?/td> 389K
代理商: M58MR016C
M58MR016C, M58MR016D
20/51
POWER CONSUMPTION
Power-down
The memory provides Reset/Power-down control
input RP. The Power-down function can be acti-
vated only if the relevant Read Configuration Reg-
ister bit is set to ’1’. In this case, when the RP
signal is pulled at V
SS
the supply current drops to
typically I
CC2
(see Table 26), the memory is dese-
lected and the outputs are in high impedance. If
RP is pulled to V
SS
during a Program or Erase op-
eration, this operation is aborted and the memory
content is no longer valid (see Reset/Power-down
input description).
Power-up
The memory Command Interface is reset on Pow-
er-up to Read Array. Either E or W must be tied to
V
IH
during Power-up to allow maximum security
and the possibility to write a command on the first
rising edge of W. At Power-up the device is config-
ured as:
– Page mode: (CR15 = 1)
– Power-down disabled: (CR10 = 0)
– BINV disabled: (CR14 = 0).
All blocks are protected and unlocked.
V
DD
, V
DDQ
and V
PP
are independent power sup-
plies and can be biased in any order.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the V
DD
rails decoupled with a 0.1μF capac-
itor close to the V
DD
, V
DDQ
and V
SS
pins. The PCB
trace widths should be sufficient to carry the re-
quired V
DD
program and erase currents.
Figure 6. X-Latency Configuration Sequence
AI05233
A19-A16
VALID ADDRESS
K
L
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
VALID DATA
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
VALID DATA
VALID DATA
CONFIGURATION CODE 4
CONFIGURATION CODE 3
CONF. CODE 2
VALID DATA
VALID DATA
VALID DATA
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相關代理商/技術參數
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