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參數(shù)資料
| 型號： | M58MR016C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 16兆1兆x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 14/51頁 |
| 文件大?。?/td> | 389K |
| 代理商： | M58MR016C |
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M58MR016C, M58MR016D
14/51
Table 12. Status Register Bits
Note:
Logic level ’1’ is V
IH
and ’0’ is V
IL
.
Mnemonic
Bit
Name
Logic
Level
Definition
Note
P/ECS
7
P/ECS
Status
1
Ready
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits b4 or b5 for Program or Erase
Success.
0
Busy
ESS
6
Erase
Suspend
Status
1
Suspended
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until
an Erase Resume instruction is given.
0
In Progress or
Completed
ES
5
Erase
Status
1
Erase Error
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
0
Erase Success
PS
4
Program
Status
1
Program Error
PS bit set to ’1’ if the P/E.C. has failed to
program a word.
0
Program
Success
VPPS
3
V
PP
Status
1
V
PP
Invalid,
Abort
VPPS bit is set if the V
PP
voltage is below
V
PPLK
when a Program or Erase instruction is
executed. V
PP
is sampled only at the beginning
of the erase/program operation.
0
V
PP
OK
PSS
2
Program
Suspend
Status
1
Suspended
On a program Suspend instruction P/ECS and
PSS bits are set to ’1’. PSS remains ’1’ until a
Program Resume Instruction is given.
0
In Progress or
Completed
BPS
1
Block
Protection
Status
1
Program/Erase
on protected
Block, Abort
BPS bit is set to ’1’ if a Program or Erase
operation has been attempted on a protected
block.
0
No operation to
protected blocks
0
Reserved
must be issued to reset b5, b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the bank in programming accepts only the RSR
(Read Status Register) and PES (Program/Erase
Suspend) instructions. See Figure 16 for Program
Flowchart and Pseudo Code.
Double Word Program (DPG)
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. The first command must be given to the
target block and only one partition can be pro-
grammed at a time; the other partition must be in
one of the read modes or in the erase suspended
mode (see Table 8).
The two words must differ only for the address A0.
Programming should not be attempted when V
PP
is not at V
PPH
. The operation can also be executed
if V
PP
is below V
PPH
but result could be uncertain.
These instruction uses three write cycles. The first
command written is the Double Word Program
Set-Up command 30h. A second write operation
latches the Address and the Data of the first word
to be written, the third write operation latches the
Address and the Data of the second word to be
written and starts the P/E.C. (see Table 11).
Read operations in the targeted bank output the
Status Register content after the programming
has started. The Status Register bit b7 returns ’0’
while the programming is in progress and ’1’ when
it has completed. After completion the Status reg-
ister bit b4 returns ’1’ if there has been a Program
Failure. Status register bit b1 returns ’1’ if the user
is attempting to program a protected block. Status
Register bit b3 returns a ’1’ if V
PP
is below V
PPLK
.
Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set). (See Table 12).
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