參數(shù)資料
型號: M58MR016C
廠商: 意法半導(dǎo)體
英文描述: 16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 16兆1兆x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 39/51頁
文件大?。?/td> 389K
代理商: M58MR016C
39/51
M58MR016C, M58MR016D
Figure 15. Reset and Power-up AC Waveforms
AI05242
W,
VDD, VDDQ
tPLPH
E, G
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
tVDHPH
RP
L,
Power-up
Table 31. Reset and Power-up AC Characteristics
Note: 1. The device Reset is possible but not guaranteed if t
PLPH
< 100ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.
Table 32. Program, Erase Times and Program, Erase Endurance Cycles
(T
A
= –40 to 85°C; V
DD
= V
DDQ
= 1.7V to 2.0V, V
PP
= V
DD
unless otherwise specified)
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
3. Same timing value if V
PP
= 12V.
Symbol
Parameter
Test Condition
Min
Unit
t
PLPH (1,2)
RP Pulse Width
100
ns
t
PHEL
t
PHLL
t
PHWL
Reset High to Device Enabled
During Program and Erase
50
μs
Other Conditions
30
ns
t
VDHPH (3)
Supply Valid to Reset High
50
μs
Parameter
Min
Max
(1)
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 K-Word) Erase (Preprogrammed)
2.5
0.5
1
sec
Main Block (32 K-Word) Erase (Preprogrammed)
10
1
3
sec
Bank Erase (Preprogrammed, Bank A)
4
sec
Bank Erase (Preprogrammed, Bank B)
15
sec
Chip Program
(2)
40
sec
Chip Program (DPG, V
PP
= 12V)
(2)
20
sec
Word Program
(3)
200
10
10
μs
Double Word Program
200
10
10
μs
Tetra Word Program
200
10
10
μs
Program/Erase Cycles (per Block)
100,000
cycles
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