參數(shù)資料
型號(hào)： MCIMX31_07
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Multimedia Applications Processors
中文描述： 多媒體應(yīng)用處理器
文件頁(yè)數(shù)： 10/108頁(yè)
文件大?。?/td> 1235K
代理商： MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
10
Freescale Semiconductor
Electrical Characteristics
4
Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX31 and
i.MX31L.
4.1
i.MX31 and i.MX31L Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See
Table 4
for a quick reference
to the individual tables and sections.
CAUTION
Stresses beyond those listed under
“Table 5, "Absolute Maximum Ratings,"
on page 10
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under
“Table 7, "Operating Ranges," on
page 12
is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
Table 4. i.MX31/i.MX31L Chip-Level Conditions
For these characteristics, …
Topic appears …
Table 5, “Absolute Maximum Ratings”
on page 10
Table 7, “Operating Ranges”
on page 12
Table 8, “Interface Frequency”
on page 13
Section 4.1.1, “Supply Current Specifications”
on page 14
Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions”
on page 14
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Supply Voltage (Core)
QVCC
max
NVCC
max
V
Imax
T
storage
-0.5
1.65
V
Supply Voltage (I/O)
-0.5
3.3
V
Input Voltage Range
-0.5
NVCC +0.3
V
Storage Temperature
-40
125
o
C
ESD Damage Immunity:
V
esd
V
Human Body Model (HBM)
–
2000
Machine Model (MM)
–
200
Charge Device Model (CDM)
–
500
Offset voltage allowed in run mode between core supplies.
V
core_offset1
1
The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4.
–
15
mV
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