參數(shù)資料
型號(hào): MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁(yè)數(shù): 43/108頁(yè)
文件大?。?/td> 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
43
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
NOTE
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
Table 31
indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Figure 34. SDRAM Refresh Timing Diagram
SD13
Data setup time
tDS
2.0
ns
SD14
Data hold time
tDH
1.3
ns
1
SD11 and SD12 are determined by SDRAM controller register settings.
Table 31. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS
CAS
WE
RAS
ADDR
BA
ROW/BA
SD6
SD7
SD11
SD10
SD10
SDCLK
SD1
SD2
SDCLK
SD3
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