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參數資料
| 型號： | MCIMX31_07 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Multimedia Applications Processors |
| 中文描述： | 多媒體應用處理器 |
| 文件頁數： | 21/108頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | MCIMX31_07 |
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Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
21
4.3.5
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA specification.
The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
Table 20
shows ATA
timing parameters.
Table 19. WR1/RD Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Units
OW7
Write 1 / Read Low Time
t
LOW1
1
5
15
μs
OW8
Transmission Time Slot
t
SLOT
60
117
120
μs
OW9
Release Time
t
RELEASE
15
–
45
μs
Table 20. ATA Timing Parameters
Name
Description
Value/
Contributing Factor
1
T
Bus clock period (ipg_clk_ata)
peripheral clock
frequency
ti_ds
Set-up time
ata_data
to
ata_iordy
edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
ti_dh
hold time
ata_iordy
edge to
ata_data
(UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
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相關代理商/技術參數 |
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| MCIMX31ADSE | 功能描述:KIT DEV ADS I.MX31 RoHS:是 類別:編程器，開發(fā)系統 >> 過時/停產零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關產品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| MCIMX31ADSE/C | 功能描述:開發(fā)板和工具包 - ARM I.MX31 APP DEV SYS RoHS:否 制造商:Arduino 產品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX31ADSE/C | 制造商:Freescale Semiconductor 功能描述:Development Kit |
| MCIMX31C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors |
| MCIMX31C_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors for Industrial and Automotive Products |
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