參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應用處理器
文件頁數(shù): 14/108頁
文件大小: 1235K
代理商: MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
14
Freescale Semiconductor
Electrical Characteristics
4.1.1
Supply Current Specifications
Table 10
shows the core current consumption for the i.MX31 and i.MX31L.
Table 10. Current Consumption
1, 2
4.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX31/i.MX31L board design must comply with the power-up and power-down sequence
guidelines as described in this section to guarantee reliable operation of the device. Any deviation from
these sequences may result in any or all of the following situations:
Cause excessive current during power up phase.
Prevent the device from booting.
Cause irreversible damage to the i.MX31/i.MX31L (worst-case scenario).
1
Typical column: TA = 25
°
C
2
Maximum column: TA = 70
°
C
Mode
Conditions
QVCC
(Peripheral)
QVCC1
(ARM)
QVCC4
(L2)
FVCC + MVCC
+ SVCC + UVCC
(PLL)
Unit
Typ
Max
Typ
Max
Typ
Max
Typ
Max
State
Retention
QVCC and QVCC1 = 0.95 V
L2 caches are power gated (QVCC4 = 0 V)
All PLLs are off, VCC = 1.4 V
ARM is in well bias
FPM is off
32 kHz input is on
CKIH input is off
CAMP is off
TCK input is off
All modules are off
No external resistive loads
RNGA oscillator is off
0.8
0.5
0.04
mA
Wait
QVCC,QVCC1, and QVCC4 = 1.22 V
ARM is in wait for interrupt mode
MAX is active
L2 cache is stopped but powered
MCU PLL is on (532 MHz), VCC = 1.4 V
USB PLL and SPLL are off, VCC = 1.4 V
FPM is on
CKIH input is on
CAMP is on
32 kHz input is on
All clocks are gated off
All modules are off
(by programming CGR[2:0] registers)
RNGA oscillator is off
No external resistive loads
6.0
3.0
0.04
3.5
mA
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