參數(shù)資料
型號(hào): MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁(yè)數(shù): 44/108頁(yè)
文件大?。?/td> 1235K
代理商: MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
44
Freescale Semiconductor
Electrical Characteristics
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
NOTE
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
Table 32
indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 32. SDRAM Refresh Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
SD3
SDRAM clock cycle time
tCK
7.5
ns
SD6
Address setup time
tAS
1.8
ns
SD7
Address hold time
tAH
1.8
ns
SD10
Precharge cycle period
1
1
SD10 and SD11 are determined by SDRAM controller register settings.
tRP
1
4
clock
SD11
Auto precharge command period
1
tRC
2
20
clock
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