參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 27/108頁
文件大小: 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
27
4.3.5.4 UDMA Out Timing
Figure 16
shows timing when the UDMA out transfer starts,
Figure 17
shows timing when the UDMA out
host terminates transfer,
Figure 18
shows timing when the UDMA out device terminates transfer, and
Table 25
lists the timing parameters for UDMA out burst.
Figure 16. UDMA Out Transfer Starts Timing Diagram
tcyc
tc1
(tcyc - tskew) > T
T big enough
trp
trp
trp (min) = time_rp * T - (tskew1 + tskew2 + tskew6)
time_rp
tx1
1
(time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive)
time_rp
tmli
tmli1
tmli1 (min) = (time_mlix + 0.4) * T
time_mlix
tzah
tzah
tzah (min) = (time_zah + 0.4) * T
time_zah
tdzfs
tdzfs
tdzfs = (time_dzfs * T) - (tskew1 + tskew2)
time_dzfs
tcvh
tcvh
tcvh = (time_cvh *T) - (tskew1 + tskew2)
time_cvh
ton
toff
ton = time_on * T - tskew1
toff = time_off * T - tskew1
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff big enough to avoid bus contention
Table 24. UDMA In Burst Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 13
,
Figure 14
,
Figure 15
Description
Controlling Variable
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