參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 54/108頁
文件大?。?/td> 1235K
代理商: MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
54
Freescale Semiconductor
Electrical Characteristics
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 44. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 45
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 45. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 46
depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
DISPB_D3_CLK
1
2
3
m
m-1
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_CLK
IP7
IP9
IP10
IP8
Start of line
IP5
IP6
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