參數(shù)資料
型號(hào): MCIMX31_07
廠(chǎng)商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁(yè)數(shù): 34/108頁(yè)
文件大?。?/td> 1235K
代理商: MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
34
Freescale Semiconductor
Electrical Characteristics
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
NOTE
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.3.9.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising
edge or falling edge according to corresponding assertion/negation control fields. Address always begins
related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according
to control register configuration. Output data begins related to BCLK rising edge except in muxed mode
where both rising and falling edge may be used according to control register configuration. Input data,
ECB and DTACK all captured according to BCLK rising edge time.
Figure 25
depicts the timing of the
WEIM module, and
Table 29
lists the timing parameters.
NF7
NFALE Hold Time
tALH
T–3.0 ns
27
ns
NF8
Data Setup Time
tDS
T
30
ns
NF9
Data Hold Time
tDH
T–5.0 ns
25
ns
NF10 Write Cycle Time
tWC
2T
60
ns
NF11 NFWE Hold Time
tWH
T–2.5 ns
27.5
ns
NF12 Ready to NFRE Low
tRR
6T
180
ns
NF13 NFRE Pulse Width
tRP
1.5T
45
ns
NF14 READ Cycle Time
tRC
2T
60
ns
NF15 NFRE High Hold Time
tREH
0.5T–2.5 ns
12.5
ns
NF16 Data Setup on READ
tDSR
N/A
10
ns
NF17 Data Hold on READ
tDHR
N/A
0
ns
1
The flash clock maximum frequency is 50 MHz.
2
Subject to DPLL jitter specification on
Table 27, "DPLL Specifications," on page 31
.
Table 28. NFC Timing Parameters
1
(continued)
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle
2
Example Timing for
NFC Clock
33 MHz
T = 30 ns
Unit
Min
Max
Min
Max
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