參數(shù)資料
型號(hào)： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 104/116頁
文件大小： 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
104 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
15.2.3
Digital test signals
Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A
digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits.
The signals selected by the TestDigiSignalSel[6:0] bits are shown in
Table 166
.
Table 166. Digital test signal selection
TestDigiSignalSel
[6:0]
F4h
E4h
If test signals are not used, the TestDigiSelect register address value must be 00h.
Remark:
All other values for TestDigiSignalSel[6:0] are for production test purposes only.
15.2.4
Examples of ISO/IEC 14443 A analog and digital test signals
Figure 27
shows a MIFARE card’s answer to a request command using the Q-clock
receiving path. RX reference is given to show the Manchester modulated signal on pin
RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ were generated in the correlation circuitry. They are processed further in the
evaluation and digitizer circuitry.
B
C
D
E
F
VEvalR
VTemp
reserved
reserved
reserved
evaluation signal from the right half-bit
temperature voltage derived from band gap
reserved for future use
reserved for future use
reserved for future use
Table 165. Analog test signal selection
…continued
Value
Signal Name
Description
Signal name
Description
s_data
s_valid
data received from the card
when logic 1 is returned the s_data and s_coll signals are
valid
when logic 1 is returned a collision has been detected in the
current bit
internal serial clock:
during transmission, this is the encoder clock
during reception this is the receiver clock
internal synchronized read signal which is derived from the
parallel microprocessor interface
internal synchronized write signal which is derived from the
parallel microprocessor interface
internal 13.56 MHz clock
BPSK output signal
BPSK signal’s amplitude detected
output as defined by the MFOUTSelect register
MFOUTSelect[2:0] bits routed to pin MFOUT
D4h
s_coll
C4h
s_clock
B5h
rd_sync
A5h
wr_sync
96h
83h
E2h
00h
int_clock
BPSK_out
BPSK_sig
no test signal
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