參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 113/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
113 of 116
continued >>
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
Table 136. Communication error table . . . . . . . . . . . . . . .81
Table 137. Transceive command 1Eh . . . . . . . . . . . . . . .82
Table 138. Meaning of ModemState . . . . . . . . . . . . . . . . .82
Table 139. WriteE2 command 01h . . . . . . . . . . . . . . . . . .84
Table 140. ReadE2 command 03h . . . . . . . . . . . . . . . . . .86
Table 141. LoadConfig command 07h . . . . . . . . . . . . . . .86
Table 142. CalcCRC command 12h . . . . . . . . . . . . . . . . .87
Table 143. CRC coprocessor parameters . . . . . . . . . . . .87
Table 144. ErrorFlag register error flags overview . . . . . .88
Table 145. LoadKeyE2 command 0Bh . . . . . . . . . . . . . . .88
Table 146. LoadKey command 19h . . . . . . . . . . . . . . . . .88
Table 147. Authent1 command 0Ch . . . . . . . . . . . . . . . . .89
Table 148. Authent2 command 14h . . . . . . . . . . . . . . . . .89
Table 149. Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .90
Table 150. Operating condition range . . . . . . . . . . . . . . . .90
Table 151. Current consumption . . . . . . . . . . . . . . . . . . . .91
Table 152. Standard input pin characteristics . . . . . . . . . .91
Table 153. Schmitt trigger input pin characteristics . . . . .91
Table 154. RSTPD input pin characteristics . . . . . . . . . . .92
Table 155. RX input capacitance and input
voltage range . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 156. Digital output pin characteristics . . . . . . . . . . . 92
Table 157. Antenna driver output pin characteristics . . . . 93
Table 158. Timing specification for separate read/write
strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 159. Common read/write strobe timing
specification . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 160. Common read/write strobe timing
specification for EPP . . . . . . . . . . . . . . . . . . . . 95
Table 161. SPI timing specification . . . . . . . . . . . . . . . . . 97
Table 162. Clock frequency . . . . . . . . . . . . . . . . . . . . . . . 97
Table 163. EEPROM characteristics . . . . . . . . . . . . . . . . 98
Table 164. Signal routed to pin MFOUT . . . . . . . . . . . . 101
Table 165. Analog test signal selection . . . . . . . . . . . . . 103
Table 166. Digital test signal selection . . . . . . . . . . . . . . 104
Table 167. Abbreviations and acronyms . . . . . . . . . . . . 107
Table 168. Revision history . . . . . . . . . . . . . . . . . . . . . . 108
23. Figures
Fig 1.
Fig 2.
Fig 3.
MFRC531 block diagram. . . . . . . . . . . . . . . . . . . .4
MFRC531 pin configuration. . . . . . . . . . . . . . . . . .5
Connection to microprocessor: separate
read and write strobes . . . . . . . . . . . . . . . . . . . . . .8
Connection to microprocessor: common
read and write strobes . . . . . . . . . . . . . . . . . . . . . .9
Connection to microprocessor: EPP common
read/write strobes and handshake. . . . . . . . . . . . .9
Connection to microprocessor: SPI . . . . . . . . . . .10
Key storage format . . . . . . . . . . . . . . . . . . . . . . .16
Timer module block diagram . . . . . . . . . . . . . . . .23
The StartUp procedure. . . . . . . . . . . . . . . . . . . . .27
Fig 10. Quartz clock connection . . . . . . . . . . . . . . . . . . .29
Fig 11. Receiver circuit block diagram. . . . . . . . . . . . . . .33
Fig 12. Automatic Q-clock calibration . . . . . . . . . . . . . . .34
Fig 13. Serial signal switch block diagram. . . . . . . . . . . .36
Fig 14. Crypto1 key handling block diagram . . . . . . . . . .40
Fig 15. Transmitting bit oriented frames . . . . . . . . . . . . .77
Fig 16. Timing for transmitting byte oriented frames . . . .78
Fig 17. Timing for transmitting bit oriented frames. . . . . .78
Fig 18. Card communication state diagram. . . . . . . . . . .83
Fig 19. EEPROM programming timing diagram. . . . . . . .85
Fig 20. Separate read/write strobe timing diagram . . . . .94
Fig 21. Common read/write strobe timing diagram . . . . .95
Fig 22. Timing diagram for common read/write strobe;
EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Fig 23. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .97
Fig 24. Application example circuit diagram: directly
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
matched antenna . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig 25. TX control signals . . . . . . . . . . . . . . . . . . . . . . . 102
Fig 26. RX control signals . . . . . . . . . . . . . . . . . . . . . . . 103
Fig 27. ISO/IEC 14443 A receiving path Q-clock . . . . . 105
Fig 28. Package outline SOT287-1. . . . . . . . . . . . . . . . 106
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