參數資料
型號: MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網絡
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數: 95/116頁
文件大小: 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
95 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
13.4.3
EPP bus timing
Table 160. Common read/write strobe timing specification for EPP
Symbol
Parameter
t
ASLASH
address strobe LOW time
t
AVASH
address valid to address strobe
HIGH time
t
ASHAV
address valid after address strobe
HIGH time
t
SLDSL
chip select LOW to data strobe
LOW time
t
DSHSH
data strobe HIGH to chip select
HIGH time
t
DSLDV
data strobe LOW to data input valid
time
t
AVDSL
address valid to data strobe LOW
time
address hold after read HIGH time
data strobe HIGH time
30
-
-
ns
t
RHAX
t
DSHDSL
8
150
-
-
-
-
ns
ns
period between
write sequences
t
WLDSL
write LOW to data strobe LOW time R/NW valid to
NDS LOW
8
-
-
ns
Fig 21. Common read/write strobe timing diagram
Table 159. Common read/write strobe timing specification
…continued
Symbol
Parameter
Conditions
Min
Typ
Max Unit
001aaj639
t
SLDSL
t
DSHSH
t
DSHDSL
t
DSHQX
t
DSHDZ
t
DSLDV
t
DSLQV
t
AVDSL
t
RHAX
t
LLAX
t
AVLL
t
DSLDSH
t
LLDSL
t
DSHDSL
t
LHLL
t
WLDSL
t
DSHRWX
A0 to A2
A0 to A2
D0 to D7
D0 to D7
NRD
R/NW
NCS/NDS
ALE
A0 to A2
Multiplexed address bus
Separated address bus
Conditions
nAStrb
multiplexed address
bus set-up time
multiplexed address
bus hold time
NCS LOW to nDStrb
LOW
nDStrb HIGH to
NCS HIGH
read cycle
Min
20
15
Typ
-
-
Max Unit
-
-
ns
ns
8
-
-
ns
0
-
-
ns
0
-
-
ns
-
-
65
ns
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