參數(shù)資料
型號(hào): MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù): 79/116頁
文件大?。?/td> 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
79 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
Figure 17
also shows write access to the FIFOData register just before the FIFO buffer’s
status is checked. This leads to FIFO empty state being held LOW which keeps the
accept further data active. The new byte written to the FIFO buffer is transmitted using the
RF interface.
Accept further data is only changed by the check FIFO empty function. This function
verifies FIFO empty for one bit duration before the last expected bit transmission.
Table 133. Transmission of frames of more than 64 bytes
Frame definition
8-bit with parity
8-bit without parity
x-bit without parity
11.2.2
Receive command 16h
Table 134. Receive command 16h
Command
The Receive command activates the receiver circuitry. All data received from the RF
interface is written to the FIFO buffer. The Receive command can be started either using
the microprocessor or automatically during execution of the Transceive command.
Remark:
This command can only be used for test purposes since there is no timing
relationship to the Transmit command.
11.2.2.1
Using the Receive command
After starting the Receive command, the internal state machine decrements to the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming
signal at the RF interface.
When the signal strength reaches a level higher than the RxThreshold register
MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can no
longer be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating
receive termination.
The different phases of the receive sequence are monitored using the PrimaryStatus
register ModemState[2:0] bits; see
Section 11.2.4 on page 82
.
Remark:
Since the counter values from 3 to 0 are needed to initialize the analog receiver
circuitry, the minimum value for RxWait[7:0] is 3.
11.2.2.2
RF channel redundancy and framing
The decoder expects the SOF pattern at the beginning of each data stream. When the
SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data
bits. Every completed byte is forwarded to the FIFO buffer.
Verification at:
8
th
bit
7
th
bit
(x
1)
th
bit
Value
Action
Arguments
and data
-
Returned
data
data stream
Receive
16h
activates receiver circuitry
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