參數(shù)資料
型號(hào)： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 33/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
33 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90
°
between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1
Receiver circuit block diagram
Figure 11
shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see
Section 9.10.2.1 on page 33
).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in
Figure 11
. One
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page 103
.
9.10.2
Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
device to MIFARE card data communication. However, in some environments specific
user settings will achieve better performance.
9.10.2.1
Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90
°
phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90
°
. After
the reset phase, a calibration procedure is automatically performed.
Fig 11. Receiver circuit block diagram
001aak615
ClkQDelay[4:0]
ClkQCalib
ClkQ180Deg
BitPhase[7:0]
CORRELATION
CIRCUITRY
EVALUATION
AND
DIGITIZER
CIRCUITRY
MinLevel[3:0]
CollLevel[3:0]
RxWait[7:0]
RcvClkSell
s_valid
s_data
s_coll
s_clock
Gain[1:0]
to
TestAnaOutSel
clock
I TO Q
CONVERSION
I-clock
Q-clock
13.56 MHz
DEMODULATOR
RX
VCorrDI
VCorrNI
VCorrDQ
VCorrNQ
VEvalR
VEvalL
VRxFollQ
VRxFollI
VRxAmpI
VRxAmpQ
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參數(shù)描述
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