MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
114 of 116
continued >>
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
24. Contents
1
2
3
3.1
4
5
6
7
8
8.1
9
9.1
9.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview of supported microprocessor
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic microprocessor interface detection . 7
Connection to different microprocessor types . 8
Separate read and write strobe . . . . . . . . . . . . 8
Common read and write strobe . . . . . . . . . . . . 9
Common read and write strobe:
EPP with handshake . . . . . . . . . . . . . . . . . . . . 9
Serial Peripheral Interface . . . . . . . . . . . . . . . . 9
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory organization of the EEPROM . . . . . . 12
Product information field (read only). . . . . . . . 13
Register initialization files (read/write) . . . . . . 13
StartUp register initialization file (read/write) . 14
Factory default StartUp register
initialization file . . . . . . . . . . . . . . . . . . . . . . . . 14
Register initialization file (read/write) . . . . . . . 16
Crypto1 keys (write only) . . . . . . . . . . . . . . . . 16
Key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Storage of keys in the EEPROM . . . . . . . . . . 17
FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Accessing the FIFO buffer . . . . . . . . . . . . . . . 17
Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Controlling the FIFO buffer. . . . . . . . . . . . . . . 18
FIFO buffer status information . . . . . . . . . . . . 18
FIFO buffer registers and flags. . . . . . . . . . . . 19
Interrupt request system. . . . . . . . . . . . . . . . . 19
Interrupt sources overview . . . . . . . . . . . . . . . 19
Interrupt request handling. . . . . . . . . . . . . . . . 20
Controlling interrupts and getting their status. 20
Accessing the interrupt registers . . . . . . . . . . 20
Configuration of pin IRQ. . . . . . . . . . . . . . . . . 21
Register overview interrupt request system . . 21
9.1.2
9.1.3
9.1.3.1
9.1.3.2
9.1.3.3
9.1.4
9.1.4.1
9.1.4.2
9.2
9.2.1
9.2.2
9.2.2.1
9.2.2.2
9.2.2.3
9.2.3
9.2.3.1
9.2.3.2
9.3
9.3.1
9.3.1.1
9.3.2
9.3.3
9.3.4
9.4
9.4.1
9.4.2
9.4.2.1
9.4.2.2
9.4.3
9.4.4
9.5
9.5.1
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
Timer unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timer unit implementation . . . . . . . . . . . . . . . 23
Timer unit block diagram . . . . . . . . . . . . . . . . 23
Controlling the timer unit . . . . . . . . . . . . . . . . 23
Timer unit clock and period . . . . . . . . . . . . . . 24
Timer unit status. . . . . . . . . . . . . . . . . . . . . . . 24
Using the timer unit functions. . . . . . . . . . . . . 25
Time-out and WatchDog counters . . . . . . . . . 25
Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programmable one shot timer and
periodic trigger . . . . . . . . . . . . . . . . . . . . . . . . 25
Timer unit registers . . . . . . . . . . . . . . . . . . . . 25
Power reduction modes . . . . . . . . . . . . . . . . . 26
Hard power-down. . . . . . . . . . . . . . . . . . . . . . 26
Soft power-down mode . . . . . . . . . . . . . . . . . 26
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 27
Automatic receiver power-down. . . . . . . . . . . 27
StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 27
Hard power-down phase . . . . . . . . . . . . . . . . 27
Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Initialization phase . . . . . . . . . . . . . . . . . . . . . 28
Initializing the parallel interface type . . . . . . . 28
Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 29
Transmitter pins TX1 and TX2. . . . . . . . . . . . 29
Configuring pins TX1 and TX2. . . . . . . . . . . . 29
Antenna operating distance versus power
consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Antenna driver output source resistance . . . . 30
Source resistance table . . . . . . . . . . . . . . . . . 31
Calculating the relative source resistance . . . 32
Calculating the effective source resistance . . 32
Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 32
Receiver circuit block diagram. . . . . . . . . . . . 33
Receiver operation. . . . . . . . . . . . . . . . . . . . . 33
9.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 33
9.10.2.2 Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 35
9.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 35
9.11
Serial signal switch . . . . . . . . . . . . . . . . . . . . 35
9.11.1
Serial signal switch block diagram. . . . . . . . . 36
9.11.2
Serial signal switch registers . . . . . . . . . . . . . 36
9.11.2.1 Active antenna concept . . . . . . . . . . . . . . . . . 37
9.11.2.2 Driving both RF parts. . . . . . . . . . . . . . . . . . . 38
9.12
MIFARE higher baud rates. . . . . . . . . . . . . . . 38
9.13
ISO/IEC 14443 B communication scheme. . . 39
9.14
MIFARE authentication and Crypto1 . . . . . . . 40
9.14.1
Crypto1 key handling. . . . . . . . . . . . . . . . . . . 40
9.5.3
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.8
9.9
9.9.1
9.9.2
9.9.3
9.9.3.1
9.9.3.2
9.9.3.3
9.9.4
9.10
9.10.1
9.10.2