參數(shù)資料
型號(hào)： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 27/116頁
文件大小： 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
27 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
9.6.3
Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4
Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
9.7 StartUp phase
The events executed during the StartUp phase are shown in
Figure 9
.
9.7.1
Hard power-down phase
The hard power-down phase is active during the following cases:
a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when V
DDD
or V
DDA
is below the digital reset threshold.
a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100
μ
s (t
PD
≥
100
μ
s). Shorter phases will not
necessarily result in the reset phase (t
reset
). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
Remark:
In case two, HIGH level on pin RSTPD, has to be at least 100
μ
s long (t
PD
≥
100
μ
s). Shorter phases will not necessarily result in the reset phase t
reset
. The slew rate of
rising/falling edge on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger
input.
Fig 9.
The StartUp procedure
001aak613
StartUp phase
states
t
RSTPD
t
reset
t
init
Hard power-
down phase
Reset phase
Initialising
phase
ready
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