參數(shù)資料
型號: MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù): 56/116頁
文件大?。?/td> 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
56 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
10.5.2.8
BitFraming register
Adjustments for bit oriented frames.
Table 67.
Bit
Symbol
Access
Table 68.
Bit
7
6 to 4 RxAlign[2:0]
BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
7
6
5
4
0
RxAlign[2:0]
R/W
D
3
0
2
1
0
TxLastBits[2:0]
D
R/W
BitFraming register bit descriptions
Symbol
Value
0
-
Description
reserved
defines the bit position for the first bit received to be stored in
the FIFO buffer. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
000
001
...
111
the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0
reserved
defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
3
2 to 0 TxLastBits[2:0]
0
-
-
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