參數(shù)資料
型號(hào): MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù): 66/116頁
文件大?。?/td> 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
66 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
[1]
When used with ISO/IEC 14443 A, this bit must be set to logic 1.
10.5.5.4
CRCPresetLSB register
LSB of the preset value for the CRC register.
Table 100. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
Bit
7
6
5
4
Symbol
CRCPresetLSB[7:0]
Access
Table 101. CRCPresetLSB register bit descriptions
Bit
Symbol
7 to 0
CRCPresetLSB[7:0]
10.5.5.5
CRCPresetMSB register
MSB of the preset value for the CRC register.
Table 102. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
Bit
7
6
5
Symbol
Access
Table 103. CRCPresetMSB bit descriptions
Bit
Symbol
7 to 0 CRCPresetMSB[7:0]
10.5.5.6
PreSet25 register
Table 104. PreSet25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
Symbol
Access
Remark:
These values must not be changed.
1
ParityOdd
1
0
1
odd parity is generated or expected
[1]
even parity is generated or expected
a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
no parity bit is inserted or expected (ISO/IEC 14443 B)
0
ParityEn
0
Table 99.
Bit
ChannelRedundancy bit descriptions
…continued
Symbol
Value
Function
3
2
1
0
R/W
Description
defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled).
4
3
2
1
0
CRCPresetMSB[7:0]
R/W
Description
defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark:
This register is not relevant if CRC8 is set to logic 1.
4
3
2
1
0
0000000
RW
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